High performance circuits, especially those used for radio frequency chips, favor the use of heterojunction bipolar transistors (HBTs) to provide high maximum oscillation frequency fMAX and cutoff frequency fT. HBTs have a structure in which the base of the transistor includes a relatively thin layer of single-crystal semiconductor alloy material. As an example, an HBT fabricated on a substrate of single-crystal silicon can have a single-crystal base formed of silicon germanium (SiGe) having a substantial proportion of germanium content and profile to improve high speed performance. Such HBT is commonly referred to as a SiGe HBT.
The juxtaposition of alloy semiconductor materials within a single semiconductor crystal is called a “heterojunction.” The heterojunction results in significant quasi-static field that increases the mobility of charge carriers in the base. Increased mobility, in turn, enables higher gain and cutoff frequency to be achieved than in transistors having the same semiconductor material throughout.
As provided by the prior art, differences exist among SiGe HBTs which allow them to achieve higher performance, or to be more easily fabricated. A cross-sectional view of one such prior art SiGe HBT 10 is illustrated in FIG. 1. Such non self-aligned HBT 10 can be fabricated relatively easily, but other designs provide better performance. As depicted in FIG. 1, the HBT 10 includes an intrinsic base 12, which is disposed in vertical relation between the emitter 14 and the collector 16. The intrinsic base 12 includes a single-crystal layer of SiGe (a single-crystal of silicon germanium having a substantial proportion of germanium). The SiGe layer forms a heterojunction with the collector 16 and a relatively thin layer of single-crystal silicon 13 which is typically present in the space between the SiGe layer and the emitter 14.
A raised extrinsic base 18 is disposed over the intrinsic base 12 as an annular structure surrounding the emitter 14. The purpose of the raised extrinsic base 18 is to inject a base current into the intrinsic base 12. For good performance, the interface 24 between the raised extrinsic base 18 and the intrinsic base is close to the junction between the emitter 14 and the intrinsic base 12. By making this distance small, the resistance across the intrinsic base 12 between the interface 24 and the emitter 14 is decreased, thereby reducing the base resistance Rb (hence RC delay) of the HBT 10. It is desirable that the interface 24 to the raised extrinsic base be self-aligned to the edge of the emitter 14. Such self-alignment would exist if the raised extrinsic base were spaced from the emitter 14 only by the width of one or more dielectric spacers formed on a sidewall of the raised extrinsic base 18.
However, in the HBT 10 shown in FIG. 1, the interface 24 is not self-aligned to the emitter 14, and the distance separating them is not as small or as symmetric as desirable. A dielectric landing pad, portions 21, 22 of which are visible in the view of FIG. 1, is disposed as an annular structure surrounding the emitter 14. Portions 21, 22 of the landing pad separate the raised extrinsic base 18 from the intrinsic base 12 on different sides of the emitter 14, making the two structures not self-aligned. Moreover, as shown in FIG. 1, because of imperfect alignment between lithography steps used to define the edges of portions 21 and 22 and those used to define the emitter opening, the lengths of portions 21 and 22 can become non-symmetric about the emitter opening, causing performance to vary.
The landing pad functions as a sacrificial etch stop layer during fabrication. The formation of the landing pad and its use are as follows. After forming the SiGe layer of the intrinsic base 12 by epitaxial growth onto the underlying substrate 11, a layer of silicon 13 is formed over the SiGe layer 12. A layer of silicon dioxide is deposited as the landing pad and is then photolithographically patterned to expose the layer 13 of single-crystal silicon. This photolithographic patterning defines the locations of interface 24 at the edges of landing pad portions 21, 22, which will be disposed thereafter to the left and the right of the emitter 14. A layer of polysilicon is then deposited to a desired thickness, from which layer the extrinsic base 18 will be formed.
Thereafter, an opening is formed in the polysilicon by anisotropically etching the polysilicon layer (as by a reactive ion etch) selectively to silicon dioxide, such etch stopping on the landing pad. After forming a spacer in the opening, the landing pad is then wet etched within the opening to expose silicon layer 13 and SiGe layer 12. A problem of the non-self-aligned structure of HBT 10 is high base resistance. Resistance is a function of the distance of a conductive path, divided by the cross-sectional area of the path. As the SiGe layer 12 is a relatively thin layer, significant resistance can be encountered traversing the distance under landing pad portions 21, 22 to the area under the emitter 14, such resistance limiting the high speed performance of the transistor.
FIG. 2 is a cross-sectional view illustrating another HBT 50 according to the prior art. Like HBT 10, HBT 50 includes an intrinsic base 52 having a layer of silicon germanium and an extrinsic base 58 consisting of polysilicon in contact with the single-crystal intrinsic base 52. However, unlike HBT 10, HBT 50 does not include landing pad portions 21, 22, but rather, the raised extrinsic base 58 is self-aligned to the emitter 54, the extrinsic base 58 being spaced from the emitter 54 by dielectric spacer. Self-aligned HBT structures such as HBT 50 have demonstrated high fT and fMAX as reported in Jagannathan, et al., “Self-aligned SiGe NPN Transistors with 285 GHz fMAX and 207 GHz fT in a Manufacturable Technology,” IEEE Electron Device letters 23, 258 (2002) and J. S. Rieh, et al., “SiGe HBTs with Cut-off Frequency of 350 GHz,” International Electron Device Meeting Technical Digest, 771 (2002). In such self-aligned HBT structures, the emitter 54 is self-aligned to the raised extrinsic base 58.
Two types of methods are provided in the prior art for fabricating HBTs 50 like that shown in FIG. 2. According to one approach, chemical mechanical polishing (CMP) is used to planarize the extrinsic base polysilicon over a pre-defined sacrificial emitter pedestal, as described in U.S. Pat. Nos. 5,128,271 and 6,346,453. A drawback of this method is that the extrinsic base layer thickness, hence the transistor performance, can vary significantly between small and large devices, as well as, between low and high density areas of devices due to dishing of the polysilicon during CMP.
In another approach, described in U.S. Pat. Nos. 5,494,836, 5,506,427 and 5,962,880, the intrinsic base is grown using selective epitaxy inside an emitter opening and under an overhanging polysilicon layer of the extrinsic base. In this approach, self-alignment of the emitter to the extrinsic base is achieved by the epitaxially grown material under the overhang. However, with this approach, special crystal growth techniques are required to ensure good, low-resistance contact between the intrinsic base and the extrinsic base.
It would be desirable to provide a self-aligned HBT and method for making the HBT which is more easily performed and kept within tolerances, and which, therefore, overcomes the challenges to the performance of the prior art HBT and prior art fabrication methods.